1. Field of the Invention
The present invention relates to a synchronous adder device for making synchronous addition for the power of a sampled receive signal for symbol identification, for example, in a receiver for digital communication, and more particularly to such a synchronous adder device which is realized with small circuit scale.
2. Description of the Related Art
On a receiving side in the digital communication, a receive signal level at a point of time corresponding to the instant of time of transmission of a symbol ("1" or "0") on a transmitting side is extracted from a receive signal. The extracted signal level is compared in magnitude with a threshold value to reproduce an original symbol.
In the case where digital data is transmitted in a narrow band, transmission with Nyquist characteristic is made and both a transmitting side and a receiving side generally use filters which have the same Nyquist characteristic. In such digital transmission, so long as a limiter amplifier is not used as a receiving amplifier, a symbol timing for extracting a symbol from a receive signal can be obtained from a point at which an envelope of the receive signal becomes the maximum.
On the receiving side, the receive signal is digitized at a sampling frequency which is N (integer) times as high as a symbol clock (or symbol transmission frequency). Thereafter, the square value of each sample is calculated and the square value for every N-th sample in such digitized samples is subjected to synchronous addition so that the every N-th sample providing the maximum value of addition is detected as a sample representing a transmit symbol.
In the digital communication, multivalued transmission using a plurality of subcarriers with carrier frequencies slightly shifted from a center frequency is made in order to improve the efficiency of communication. In the case of this communication system, the performance of detection of a symbol timing can be improved by using the sum of envelopes of the respective subcarriers.
The conventional synchronous adder device for performing the above-mentioned synchronous addition is shown in FIG. 1. The device includes an A/D converter 2 for digitizing an in-phase component (or I signal) 1 of a receive signal for each subcarrier at a sampling frequency which is N times as high as a symbol clock, an A/D converter 4 for digitizing an orthogonal component (or Q signal) 3 of the receive signal for each subcarrier at the above-mentioned sampling frequency, frequency converters 7 to 10 for performing frequency conversion corresponding to the respective subcarriers so that the center frequencies of digitized signals 5 or 6 of the respective subcarriers coincide with each other or both the signals 5 and the signals 6 of the respective subcarriers have the same center frequency, waveform shaping filters 11 to 18 for waveform-shaping the I and Q signals of each subcarrier having the same or coincident center frequency by use of a common filtering characteristic, squaring circuits 27 to 34 for squaring the waveform-shaped signals 19 to 26, respectively, an adder 35 for adding the outputs of the squaring circuits 27 to 34, an adding circuit 36 for adding the output of the adder 35 to the previous cumulative or integrated value of the corresponding sampling interval, a memory 37 for storing the result of addition by the adding circuit 36 separately for each sampling interval, and a decision point detecting circuit 38 for detecting a sample in a sampling interval which provides the maximum result of addition.
The device of FIG. 1 shows the construction in the case where data is transmitted through four subcarriers and the A/D conversion is made by an over-sampling of N=7 or at a sampling frequency which is seven times as high as the symbol clock.
In this synchronous adder device, data transmitted through four subcarriers is inputted to the A/D converters 2 and 4 after separation thereof into an I signal 1 and a Q signal 3 through quadrature detection. The A/D converters 2 and 4 digitize the I signal 1 and the Q signal 3, respectively, at the sampling frequency which is seven times as high as the symbol clock.
Then, the digitized I and Q signals 5 and 6 are inputted to the frequency converters 7 to 10. Since the four subcarriers have their carrier angular frequencies which are respectively shifted from the center frequency by -3.DELTA..omega., -.DELTA..omega., and 3.DELTA..omega., the frequency converters 7 to 10 subject the I signals 5 and the Q signals 6 of the respective subcarriers to frequency conversion corresponding to each subcarrier so that both the I signals 5 and the Q signals 6 of the respective subcarriers have the same center frequency. The state of such frequency conversion is illustrated in FIGS. 2A to 2C. The frequency (see FIG. 2A) shifted from the center, for example, by .+-..DELTA..omega. is moved by .-+..DELTA..omega. through the processing by the frequency converter so that the subcarrier is converted into a state shown in FIG. 2B.
Signals 39 to 46 processed by the frequency converters 7 to 10 are inputted to the waveform shaping filters 11 to 18. Each of the waveform shaping filters 11 to 18 is provided with a characteristic capable of deriving or extracting a signal in a frequency range, as shown by a square in FIG. 2B, which has a fixed width around the center frequency. As a result, a signal shown in FIG. 2C is extracted by the waveform shaping filter.
The outputs of the waveform shaping filters 11 to 18 are respectively squared by the squaring circuits 27 to 34 to determine envelopes. The outputs of the squaring circuits 27 to 34 are added by the adder 35 to determine the sum of the envelopes of the four subcarriers.
A value determined by the adder 35 is added by the adding circuit 36 to the previous value stored in the memory 37. The memory 37 has previous cumulative values stored separately for sampling intervals 1 to 7 corresponding to the number 7 of samples in the over-sampling. When a value obtained by the adder 35 is one in the sampling interval 2, the previous cumulative value of the sampling interval 2 is read from the memory 37. The read cumulative value and the value obtained by the adder 35 are added by the adding circuit 36. The result of addition is again stored into a location of the memory 37 where the cumulative value of the sampling interval 2 is to be stored.
The above addition is made for a certain time. The decision point detecting circuit 38 detects the maximum value from among the values of addition stored in the memory 37 for the respective sampling intervals as the results of addition for the certain time. A sample corresponding to a sampling interval providing the maximum value is identified as the optimum sample for symbol reproduction.
In the conventional synchronous adder device, however, it is required for the determination of the envelopes of the four subcarriers that the frequency conversion process should be performed four times and each of the filtering process and the squaring process should be performed eight times. Namely, it is necessary to perform the frequency conversion process by the number of times which is equal to the number of subcarriers and to perform each of the filtering process and the squaring process by the number of times which is twice as large as the number of subcarriers.
There is a problem that an attempt to cope with such a large quantity of frequency conversion process, filtering process and so forth by the extension of a hardware results in an increase in circuit scale and an attempt at realization by a software results in the difficulty of the processing in a real time.